[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"$fx-zv-42c7zgAcktELVxudBzz-HJj9W_2vBgaoox8IJM":3},{"answer":4,"createTime":5,"id":6,"options":7,"origin":13,"question":20,"related":21,"source":32,"type":64},[],"2024-05-19 21:28:51",144684860,[8,9,10,11,12],"PROM","CPU","CPLD","FPGA","PLA",{"count":14,"courseId":15,"courseImg":16,"courseName":17,"workId":18,"workName":19},14,"bdf94b11f423cd52ef7d39e997704ed2","https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002Feda3962f140d25822e18cf656ac29ca1.png","数字电子技术（2023-2024-2）","work_34982834","第11周作业(4.6-4.8,6.5)","下列属于可编程逻辑器件的有( )",[22,34,43,52,61,65,73,78,84,89],{"answer":23,"createTime":24,"id":25,"options":26,"question":31,"source":32,"type":33},[],"2024-05-19 19:12:07",144644537,[27,28,29,30],"通用型集成电路","专用型集成电路","片上系统","可编程逻辑器件","PLD是( )的简称","v1",0,{"answer":35,"createTime":24,"id":36,"options":37,"question":42,"source":32,"type":33},[],144644540,[38,39,40,41],"函数","指令","模块","子程序","Verilog HDL 语言采用 ( )的结构",{"answer":44,"createTime":24,"id":45,"options":46,"question":51,"source":32,"type":33},[],144644543,[47,48,49,50],"Y=AC","●表示编程连接","Y=ABC","×表示固定连接","PLD电路中如下图所示,则下列说法正确得是( ). \u003Cimg src=\"https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002F929d4b2565668f91132094837163744c.png\">",{"answer":53,"createTime":24,"id":54,"options":55,"question":60,"source":32,"type":33},[],144644546,[56,57,58,59],"1mux2_to_1","mux2$1","2选1mux","mux2*1","模块名由字母、数字及符号$,下划线_组成的标识符.下列是合法的是( )",{"answer":62,"createTime":5,"id":6,"options":63,"question":20,"source":32,"type":64},[],[8,9,10,11,12],1,{"answer":66,"createTime":5,"id":67,"options":68,"question":71,"source":32,"type":72},[],144684861,[69,70],"正确","错误","Verilog HDL 语言中各个模块是顺序执行的",3,{"answer":74,"createTime":5,"id":75,"options":76,"question":77,"source":32,"type":72},[],144684862,[69,70],"在Verilog HDL 语言中,用assign语句可以定义wire类型的信号",{"answer":79,"createTime":5,"id":80,"options":81,"question":82,"source":32,"type":83},[],144684863,[],"用VerilogHDL语言实现对题4.6(教材201-202)所要设计电路的逻辑功能的描述.已得4.6题的电路图如下所示.\u003Cimg src=\"https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002Fe4527f20e1bc2afe1a27837d5d7735cd.png\">请补充:module control (A,B,C,L,S); input A,B,C; output L,S; ( 1 ); \u002F\u002F定义G1门的输出 not G1 (Bnot,B); wire T; \u002F\u002F定义G2门的输出 ( 2 ); \u002F\u002F调用一个与门G2 nor G3 (S,A,T); buf G4 (L,B);endmoudule",2,{"answer":85,"createTime":5,"id":86,"options":87,"question":88,"source":32,"type":83},[],144684864,[],"HDL是指( )",{"answer":90,"createTime":5,"id":91,"options":92,"question":93,"source":32,"type":83},[],144684867,[],"Verilog HDL 语言中: 2'd61 表示( )进制数,其对应的二进制数为( )"]