[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"$fBX3y6lzy5lhpwNFPHZ_-EL2VwTCJZrP8lnUu1HDQVck":3},{"answer":4,"createTime":5,"id":6,"options":7,"origin":10,"question":17,"related":18,"source":29,"type":72},[],"2024-05-19 21:28:51",144684861,[8,9],"正确","错误",{"count":11,"courseId":12,"courseImg":13,"courseName":14,"workId":15,"workName":16},14,"bdf94b11f423cd52ef7d39e997704ed2","https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002Feda3962f140d25822e18cf656ac29ca1.png","数字电子技术（2023-2024-2）","work_34982834","第11周作业(4.6-4.8,6.5)","Verilog HDL 语言中各个模块是顺序执行的",[19,31,40,49,58,69,73,78,84,89],{"answer":20,"createTime":21,"id":22,"options":23,"question":28,"source":29,"type":30},[],"2024-05-19 19:12:07",144644537,[24,25,26,27],"通用型集成电路","专用型集成电路","片上系统","可编程逻辑器件","PLD是( )的简称","v1",0,{"answer":32,"createTime":21,"id":33,"options":34,"question":39,"source":29,"type":30},[],144644540,[35,36,37,38],"函数","指令","模块","子程序","Verilog HDL 语言采用 ( )的结构",{"answer":41,"createTime":21,"id":42,"options":43,"question":48,"source":29,"type":30},[],144644543,[44,45,46,47],"Y=AC","●表示编程连接","Y=ABC","×表示固定连接","PLD电路中如下图所示,则下列说法正确得是( ). \u003Cimg src=\"https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002F929d4b2565668f91132094837163744c.png\">",{"answer":50,"createTime":21,"id":51,"options":52,"question":57,"source":29,"type":30},[],144644546,[53,54,55,56],"1mux2_to_1","mux2$1","2选1mux","mux2*1","模块名由字母、数字及符号$,下划线_组成的标识符.下列是合法的是( )",{"answer":59,"createTime":5,"id":60,"options":61,"question":67,"source":29,"type":68},[],144684860,[62,63,64,65,66],"PROM","CPU","CPLD","FPGA","PLA","下列属于可编程逻辑器件的有( )",1,{"answer":70,"createTime":5,"id":6,"options":71,"question":17,"source":29,"type":72},[],[8,9],3,{"answer":74,"createTime":5,"id":75,"options":76,"question":77,"source":29,"type":72},[],144684862,[8,9],"在Verilog HDL 语言中,用assign语句可以定义wire类型的信号",{"answer":79,"createTime":5,"id":80,"options":81,"question":82,"source":29,"type":83},[],144684863,[],"用VerilogHDL语言实现对题4.6(教材201-202)所要设计电路的逻辑功能的描述.已得4.6题的电路图如下所示.\u003Cimg src=\"https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002Fe4527f20e1bc2afe1a27837d5d7735cd.png\">请补充:module control (A,B,C,L,S); input A,B,C; output L,S; ( 1 ); \u002F\u002F定义G1门的输出 not G1 (Bnot,B); wire T; \u002F\u002F定义G2门的输出 ( 2 ); \u002F\u002F调用一个与门G2 nor G3 (S,A,T); buf G4 (L,B);endmoudule",2,{"answer":85,"createTime":5,"id":86,"options":87,"question":88,"source":29,"type":83},[],144684864,[],"HDL是指( )",{"answer":90,"createTime":5,"id":91,"options":92,"question":93,"source":29,"type":83},[],144684867,[],"Verilog HDL 语言中: 2'd61 表示( )进制数,其对应的二进制数为( )"]