[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"$fnE4BjTmgYnMS-iprUKu9niF0nia4JPKjSFUYKdJzFzg":3},{"answer":4,"createTime":5,"id":6,"options":7,"origin":8,"question":15,"related":16,"source":27,"type":83},[],"2024-05-19 21:28:51",144684863,[],{"count":9,"courseId":10,"courseImg":11,"courseName":12,"workId":13,"workName":14},14,"bdf94b11f423cd52ef7d39e997704ed2","https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002Feda3962f140d25822e18cf656ac29ca1.png","数字电子技术（2023-2024-2）","work_34982834","第11周作业(4.6-4.8,6.5)","用VerilogHDL语言实现对题4.6(教材201-202)所要设计电路的逻辑功能的描述.已得4.6题的电路图如下所示.\u003Cimg src=\"https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002Fe4527f20e1bc2afe1a27837d5d7735cd.png\">请补充:module control (A,B,C,L,S); input A,B,C; output L,S; ( 1 ); \u002F\u002F定义G1门的输出 not G1 (Bnot,B); wire T; \u002F\u002F定义G2门的输出 ( 2 ); \u002F\u002F调用一个与门G2 nor G3 (S,A,T); buf G4 (L,B);endmoudule",[17,29,38,47,56,67,75,80,84,89],{"answer":18,"createTime":19,"id":20,"options":21,"question":26,"source":27,"type":28},[],"2024-05-19 19:12:07",144644537,[22,23,24,25],"通用型集成电路","专用型集成电路","片上系统","可编程逻辑器件","PLD是( )的简称","v1",0,{"answer":30,"createTime":19,"id":31,"options":32,"question":37,"source":27,"type":28},[],144644540,[33,34,35,36],"函数","指令","模块","子程序","Verilog HDL 语言采用 ( )的结构",{"answer":39,"createTime":19,"id":40,"options":41,"question":46,"source":27,"type":28},[],144644543,[42,43,44,45],"Y=AC","●表示编程连接","Y=ABC","×表示固定连接","PLD电路中如下图所示,则下列说法正确得是( ). \u003Cimg src=\"https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002F929d4b2565668f91132094837163744c.png\">",{"answer":48,"createTime":19,"id":49,"options":50,"question":55,"source":27,"type":28},[],144644546,[51,52,53,54],"1mux2_to_1","mux2$1","2选1mux","mux2*1","模块名由字母、数字及符号$,下划线_组成的标识符.下列是合法的是( )",{"answer":57,"createTime":5,"id":58,"options":59,"question":65,"source":27,"type":66},[],144684860,[60,61,62,63,64],"PROM","CPU","CPLD","FPGA","PLA","下列属于可编程逻辑器件的有( )",1,{"answer":68,"createTime":5,"id":69,"options":70,"question":73,"source":27,"type":74},[],144684861,[71,72],"正确","错误","Verilog HDL 语言中各个模块是顺序执行的",3,{"answer":76,"createTime":5,"id":77,"options":78,"question":79,"source":27,"type":74},[],144684862,[71,72],"在Verilog HDL 语言中,用assign语句可以定义wire类型的信号",{"answer":81,"createTime":5,"id":6,"options":82,"question":15,"source":27,"type":83},[],[],2,{"answer":85,"createTime":5,"id":86,"options":87,"question":88,"source":27,"type":83},[],144684864,[],"HDL是指( )",{"answer":90,"createTime":5,"id":91,"options":92,"question":93,"source":27,"type":83},[],144684867,[],"Verilog HDL 语言中: 2'd61 表示( )进制数,其对应的二进制数为( )"]