[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"$fW0Kq66rglffZo55mpzXRdlBFpRKQ-l0GdPhf1Q6uCzI":3},{"answer":4,"createTime":5,"id":6,"options":7,"origin":12,"question":19,"related":20,"source":30,"type":31},[],"2024-07-03 09:41:31",157198766,[8,9,10,11],"reg","wire","tri","不可用",{"count":13,"courseId":14,"courseImg":15,"courseName":16,"workId":17,"workName":18},10,"beafe4ca93cb149815907ddfd6cf8318","https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002F25b30343053994e8940089572d36015b.jpg","FPGA原理及应用","work_35908744","作业2","信号没有定义数据类型时,缺省为类型________",[21,32,35,45,54,64,73,82,91,100],{"answer":22,"createTime":5,"id":23,"options":24,"question":29,"source":30,"type":31},[],157198762,[25,26,27,28],"INOUT","inout","input","output","在Verilog HDL语言的端口声明语句中,用( )关键字声明端口为双向端口","v1",0,{"answer":33,"createTime":5,"id":6,"options":34,"question":19,"source":30,"type":31},[],[8,9,10,11],{"answer":36,"createTime":37,"id":38,"options":39,"question":44,"source":30,"type":31},[],"2024-07-03 09:41:32",157198768,[40,41,42,43],"X","1","Z","0","如果线网类型变量说明后未赋值,其缺省值是( )",{"answer":46,"createTime":37,"id":47,"options":48,"question":53,"source":30,"type":31},[],157198771,[49,50,51,52],"占空比为1\u002F3","clk=1","clk=0","周期为10","aways begin #5 clk=0; #10 clk=~clk; end产生的波形( )",{"answer":55,"createTime":56,"id":57,"options":58,"question":63,"source":30,"type":31},[],"2024-07-03 09:41:33",157198774,[59,60,61,62],"头文件、主函数、子函数","以module endmodule引导的模块描述、端口说明、电路功能说明","宏定义、变量定义、函数语句","函数名、输入参数、输出参数","一个Verilog HDL程序主要包含哪三部分",{"answer":65,"createTime":56,"id":66,"options":67,"question":72,"source":30,"type":31},[],157198778,[68,69,70,71],"ab@2","adcd","mux21a","_ccc","以下哪个标识符是错误的",{"answer":74,"createTime":56,"id":75,"options":76,"question":81,"source":30,"type":31},[],157198783,[77,78,79,80],"-8'd24","6'dA3","8'h57","2'b10","在Verilog中,下列整数表示错误的是( )",{"answer":83,"createTime":56,"id":84,"options":85,"question":90,"source":30,"type":31},[],157198789,[86,87,88,89],"0,15,12,3","1,14,3,12","1,13,12,3","13,1,3,12","reg[3:0]a,b; 若a=5,b=9,则a&b, a|b, a^b, a^~b 的结果依次为( )",{"answer":92,"createTime":56,"id":93,"options":94,"question":99,"source":30,"type":31},[],157198795,[95,96,97,98],"10,5","5,10","10,10","5,5","reg[3:0]a,b; 若a=5,b=10,则执行以下代码后,a和b结果依次为( ) "if(a <= b) a <= b; else b <= a;"",{"answer":101,"createTime":56,"id":102,"options":103,"question":108,"source":30,"type":31},[],157198801,[104,105,106,107],"FSM","ATM","Flip_Flop","Moore","有限状态机,也称为( ),其在任意时刻都处于有限状态集合中的一种状态"]