[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"$fG8pzg8E2T1eAqSCirhq5OUQLrst8U2Wk8jflPz2_7lQ":3},{"answer":4,"createTime":5,"id":6,"options":7,"origin":12,"question":19,"related":20,"source":30,"type":31},[],"2024-12-18 12:04:54",171970325,[8,9,10,11],"1","z","0","x",{"count":13,"courseId":14,"courseImg":15,"courseName":16,"workId":17,"workName":18},110,"50283e50aa93fcd7fc2909920a074a8d","https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002F64a5262ef47506f78f929013d410399a.jpg","verilog硬件语言与应用","work_38677079","期中考试练习题","bx = = = bx 表达式的结果为()",[21,32,41,50,59,68,77,86,95,98],{"answer":22,"createTime":5,"id":23,"options":24,"question":29,"source":30,"type":31},[],171970309,[25,26,27,28],"4'b1000","4'b0000","4'b1001","4'b1011","4'b1001>>4","v1",0,{"answer":33,"createTime":5,"id":34,"options":35,"question":40,"source":30,"type":31},[],171970311,[36,37,38,39],"FPGA","PROM","PLA","PAL","以下哪个可编程器件是基于与阵列可编程或阵列不可编程的原理",{"answer":42,"createTime":5,"id":43,"options":44,"question":49,"source":30,"type":31},[],171970313,[45,46,47,48],"电子CAD→电子CAE→EDA","电子CAE→机械CAD→EDA","CPLD→简单PLD→FPGA","ESDA→电子CAD→电子CAE","EDA发展历程,下列中那个次序是对的",{"answer":51,"createTime":5,"id":52,"options":53,"question":58,"source":30,"type":31},[],171970315,[54,55,56,57],"或阵列可编程","与阵列可编程","查找表(LUT)","与或阵列可编程","FPGA的可编程是主要基于什么结构",{"answer":60,"createTime":5,"id":61,"options":62,"question":67,"source":30,"type":31},[],171970317,[63,64,65,66],"综合","焊接","办公自动化","自动布局布线","下列哪些是可以借助计算机上的EDA软件来完成的",{"answer":69,"createTime":5,"id":70,"options":71,"question":76,"source":30,"type":31},[],171970319,[72,73,74,75],"顶层","积木式","自顶向下","自底向上","基于硬件描述语言HDL的数字系统设计目前最常用的设计法称为( )设计法",{"answer":78,"createTime":5,"id":79,"options":80,"question":85,"source":30,"type":31},[],171970321,[81,82,83,84],"基于或阵列可编程","基于与阵列可编程","基于乘积项逻辑可编程","基于LUT结构","下列关于FPGA可编程原理的说法,那个是正确的____",{"answer":87,"createTime":5,"id":88,"options":89,"question":94,"source":30,"type":31},[],171970323,[90,91,92,93],"Quartus II 13.1","LatticeXP","vivado2019","vivado2024","实验室采用的软件工具平台是",{"answer":96,"createTime":5,"id":6,"options":97,"question":19,"source":30,"type":31},[],[8,9,10,11],{"answer":99,"createTime":5,"id":100,"options":101,"question":106,"source":30,"type":31},[],171970327,[102,103,104,105],"output","Mondule","input","assign","verilog语言内部已使用的成为关键字或保留字,()不是关键字"]