[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"$fJCG_cibFHILRe2wcZxl-AGAydDGUw95-3gK9DeguYOM":3},{"answer":4,"createTime":5,"id":6,"options":7,"origin":16,"question":23,"related":24,"source":35,"type":36},[],"2023-06-16 23:43:42",66270610,[8,9,10,11,12,13,14,15],"状态化简","根据方程画出逻辑图; 检查是否自启动","求出电路的状态方程和输出方程,将状态方程和特性方程相对照,得到驱动方程","逻辑抽象,得到状态转换图","选定触发器的类型","由状态转换图得到状态转换表","状态分配","BFECADG",{"count":17,"courseId":18,"courseImg":19,"courseName":20,"workId":21,"workName":22},14,"f756b336e80f38af1ace17e94bf0d968","https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002F66f1d06f507e180dbb38a48d65920c31.jpg","数字电子技术（2022-2023-2）","work_27511145","第10-11周作业(6.3.2,6.4.1,6.5-6.6)","下列同步时序逻辑电路设计方法,正确的顺序是( ).(不加任何间隔标点)",[25,37,46,49,58,64,69,74,79,84],{"answer":26,"createTime":5,"id":27,"options":28,"question":34,"source":35,"type":36},[],66270608,[29,30,31,32,33],"S6,S7","S7,S6","S7,S7","无法确定,没有初始状态","S6,S6","现有十进制,欲实现七进制,若为同步置零,则在状态( )时产生置零信号.若为异步置零,则在状态( )时产生置零信号.(全0状态表示为S0)","v1",0,{"answer":38,"createTime":5,"id":39,"options":40,"question":45,"source":35,"type":36},[],66270609,[41,42,43,44],"4,8","8,4","2,2","6,8","4位移位寄存器构成环形计数器,其有效循环有( )个状态;构成扭环形计数器,其有效循环有( )个状态",{"answer":47,"createTime":5,"id":6,"options":48,"question":23,"source":35,"type":36},[],[8,9,10,11,12,13,14,15],{"answer":50,"createTime":5,"id":51,"options":52,"question":57,"source":35,"type":36},[],66270611,[53,54,55,56],"3","16","8","4","8个D触发器构成环形计数器,其计数长度为()",{"answer":59,"createTime":5,"id":60,"options":61,"question":62,"source":35,"type":63},[],66270612,[],"根据功能要求,补全Verilog HDL代码.CLK上升沿触发、异步清零端的JK触发器.其Verilog HDL代码如下:module jkff ( j, k, clk, reset, q ); input j, k, clk , reset; output q; reg q; wire ( ____ ) ; assign jk = { j , k }; always @( ____ or negedge reset ) begin if (~reset) q <= 1'b0; else if (jk==2'b00) q <= q; else if (jk==2'b01) q <= 1'b0; else if (jk==2'b10) q <= 1'b1; else q <= !q; endendmodule",2,{"answer":65,"createTime":5,"id":66,"options":67,"question":68,"source":35,"type":63},[],66270613,[],"欲实现模10计数器,至少需要____个触发器,若采用扭环形计数器,则需要____个触发器",{"answer":70,"createTime":5,"id":71,"options":72,"question":73,"source":35,"type":63},[],66270614,[],"下面Verilog HDL代码描述的是____电路 [答题格式:同步\u002F异 清零端的*** 触发器] ,CLK是____触发. [答题格式:高电平\u002F低电平\u002F上升沿\u002F下降沿] module dff ( d,clk,reset,q ,nq) ; input d,clk,reset ; output q,nq; reg q; always @ ( posedge clk ) begin if ( reset ) q <= 1'b0 ; else q <= d; end assign nq = !q ; endmodule",{"answer":75,"createTime":5,"id":76,"options":77,"question":78,"source":35,"type":63},[],66270615,[],"分析下图的计数器电路,采用的是( )法,第1个状态是( ),最后这个状态是( ),是( )进制的计数器. \u003Cimg src=\"https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002F7899dd8a04c48048600a330bfeea8f12.png\">",{"answer":80,"createTime":5,"id":81,"options":82,"question":83,"source":35,"type":63},[],66270616,[],"下图所示计数器电路的分频比为( ).分频比即Y与CLK的频率之比.其中第(1)片74161是( )进制计数器,第(2)片是( )进制计数器.两片构成了( )进制计数器.\u003Cimg src=\"https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002Fd46c70c8b6e0d2ff2dd1ae8db2183033.png\">",{"answer":85,"createTime":5,"id":86,"options":87,"question":88,"source":35,"type":63},[],66270617,[],"下图电路中,实现了( )进制计数器,两片之间是( )进制.\u003Cimg src=\"https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002F8394652f5f138ca161ced0077f1c2432.png\">"]