[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"$fzKXD-w35NXsWC_uUR9fZc4Z9CJ7tfbzR4NPW86pet-8":3},{"answer":4,"createTime":5,"id":6,"options":7,"origin":8,"question":15,"related":16,"source":27,"type":65},[],"2023-06-16 23:43:42",66270617,[],{"count":9,"courseId":10,"courseImg":11,"courseName":12,"workId":13,"workName":14},14,"f756b336e80f38af1ace17e94bf0d968","https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002F66f1d06f507e180dbb38a48d65920c31.jpg","数字电子技术（2022-2023-2）","work_27511145","第10-11周作业(6.3.2,6.4.1,6.5-6.6)","下图电路中,实现了( )进制计数器,两片之间是( )进制.\u003Cimg src=\"https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002F8394652f5f138ca161ced0077f1c2432.png\">",[17,29,38,51,60,66,71,76,81,86],{"answer":18,"createTime":5,"id":19,"options":20,"question":26,"source":27,"type":28},[],66270608,[21,22,23,24,25],"S6,S7","S7,S6","S7,S7","无法确定,没有初始状态","S6,S6","现有十进制,欲实现七进制,若为同步置零,则在状态( )时产生置零信号.若为异步置零,则在状态( )时产生置零信号.(全0状态表示为S0)","v1",0,{"answer":30,"createTime":5,"id":31,"options":32,"question":37,"source":27,"type":28},[],66270609,[33,34,35,36],"4,8","8,4","2,2","6,8","4位移位寄存器构成环形计数器,其有效循环有( )个状态;构成扭环形计数器,其有效循环有( )个状态",{"answer":39,"createTime":5,"id":40,"options":41,"question":50,"source":27,"type":28},[],66270610,[42,43,44,45,46,47,48,49],"状态化简","根据方程画出逻辑图; 检查是否自启动","求出电路的状态方程和输出方程,将状态方程和特性方程相对照,得到驱动方程","逻辑抽象,得到状态转换图","选定触发器的类型","由状态转换图得到状态转换表","状态分配","BFECADG","下列同步时序逻辑电路设计方法,正确的顺序是( ).(不加任何间隔标点)",{"answer":52,"createTime":5,"id":53,"options":54,"question":59,"source":27,"type":28},[],66270611,[55,56,57,58],"3","16","8","4","8个D触发器构成环形计数器,其计数长度为()",{"answer":61,"createTime":5,"id":62,"options":63,"question":64,"source":27,"type":65},[],66270612,[],"根据功能要求,补全Verilog HDL代码.CLK上升沿触发、异步清零端的JK触发器.其Verilog HDL代码如下:module jkff ( j, k, clk, reset, q ); input j, k, clk , reset; output q; reg q; wire ( ____ ) ; assign jk = { j , k }; always @( ____ or negedge reset ) begin if (~reset) q <= 1'b0; else if (jk==2'b00) q <= q; else if (jk==2'b01) q <= 1'b0; else if (jk==2'b10) q <= 1'b1; else q <= !q; endendmodule",2,{"answer":67,"createTime":5,"id":68,"options":69,"question":70,"source":27,"type":65},[],66270613,[],"欲实现模10计数器,至少需要____个触发器,若采用扭环形计数器,则需要____个触发器",{"answer":72,"createTime":5,"id":73,"options":74,"question":75,"source":27,"type":65},[],66270614,[],"下面Verilog HDL代码描述的是____电路 [答题格式:同步\u002F异 清零端的*** 触发器] ,CLK是____触发. [答题格式:高电平\u002F低电平\u002F上升沿\u002F下降沿] module dff ( d,clk,reset,q ,nq) ; input d,clk,reset ; output q,nq; reg q; always @ ( posedge clk ) begin if ( reset ) q <= 1'b0 ; else q <= d; end assign nq = !q ; endmodule",{"answer":77,"createTime":5,"id":78,"options":79,"question":80,"source":27,"type":65},[],66270615,[],"分析下图的计数器电路,采用的是( )法,第1个状态是( ),最后这个状态是( ),是( )进制的计数器. \u003Cimg src=\"https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002F7899dd8a04c48048600a330bfeea8f12.png\">",{"answer":82,"createTime":5,"id":83,"options":84,"question":85,"source":27,"type":65},[],66270616,[],"下图所示计数器电路的分频比为( ).分频比即Y与CLK的频率之比.其中第(1)片74161是( )进制计数器,第(2)片是( )进制计数器.两片构成了( )进制计数器.\u003Cimg src=\"https:\u002F\u002Ftihai-oss-cloud.itihey.com\u002Fimg\u002Fd46c70c8b6e0d2ff2dd1ae8db2183033.png\">",{"answer":87,"createTime":5,"id":6,"options":88,"question":15,"source":27,"type":65},[],[]]